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20 v, 6 a synchronous step - down regulator with low - side driver data sheet adp2381 features input voltage : 4.5 v to 20 v integrated 44 m h igh -s ide m osfet 0.6 v 1% r eference v oltage o ver t emperature contin u ous o utput c urrent: 6 a programmable switching frequency: 250 khz to 1.4 mhz synchronizes to e xternal c lock: 2 50 khz to 1.4 mhz 180 o ut - of -p hase s ynchronization programmable uvlo power -g ood o utput external c ompensation internal s oft s tart with external adjustable option start up into a p recharged o utput supported by adisimpower design tool applications communication i nfrastructure networking and s ervers industrial and i nstrumentation healthcare and m edical intermediate power rail c onversion dc - to - dc point of load a pplication typical applications circuit figure 1. figure 2. adp2381 efficiency vs . output current, v in = 12 v, f sw = 250 k hz general description the adp2381 is a current mode cont rol , synchronous , step - down , dc - to - dc regulator. it integrates a 44 m? power mosfet and a low - side driver to provide a high efficiency solution. the adp2381 runs from an input voltage of 4.5 v to 20 v and can deliver 6 a of output current. the o utput voltage can be adjust ed to 0.6 v to 90% of the input voltage. the switch ing frequency of the adp2381 can be programmed from 2 50 khz to 1.4 mhz or fixed at 29 0 khz or 5 50 khz. the synchronization functio n allows the switching frequency to be synchronized to an external clock to minimize system noise. external compensation and an adjustable soft start provide design flexibility. the power - good output provide s simple and reliable power sequencing. additiona l features include programmable undervoltage lockout (uvlo) , overvoltage protection ( ovp ), over current protection ( ocp ), and thermal shutdown (tsd) . the adp2381 operates over the ? 40 c to +125 c junction temperature range and is available in a 16 -lead tssop_ep package . adp2381 10209-001 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r osc r top r bot c ss c in c out v out c bst c vreg l v in c c_ea c cp_ea r c_ea fet 100 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 10209-002 v out = 3.3v v out = 5v v out = 1.2v rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved.
adp2381 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applications circuit ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal information ................................................................... 5 esd caution .................................................................................. 5 pin configuration and function description .............................. 6 typical performance characteristics ............................................. 7 functional block diagram ............................................................ 12 theory of operation ...................................................................... 13 control scheme .......................................................................... 13 internal regul ator (vreg) ....................................................... 13 bootstrap circuitry .................................................................... 13 low - side driver .......................................................................... 13 oscillator ..................................................................................... 13 synchronization .......................................................................... 13 enable and s oft start .................................................................. 13 power good ................................................................................. 14 peak current limit and short - circuit protection ................. 14 over v ol tage protection (ovp) .............. ................................... 14 under v o ltage lockout (uvlo) ................ ................................ 14 thermal shutdown ..................................................................... 14 applications information .............................................................. 15 input capacitor selection .......................................................... 15 output voltage setting .............................................................. 15 voltage conversion limitations ............................................... 15 inductor selection ...................................................................... 15 output capacitor selection ....................................................... 17 low - side power device selection ............................................ 17 programming input voltage uvlo ........................................ 18 compensation design ............................................................... 18 adisimpower design tool ....................................................... 19 desi gn example .............................................................................. 20 output voltage setting .............................................................. 20 frequency setting ....................................................................... 20 inductor s election ...................................................................... 20 output capacitor selection ....................................................... 20 low - side mosfet selection ................................................... 21 compensation components ..................................................... 21 soft start time program ........................................................... 21 inpu t capacitor selection .......................................................... 21 schematic for design example ................................................. 21 external components recommendation .................................... 23 circuit board layout recommendations ................................... 25 typical application circuits ......................................................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 3 /12 revision 0: initial version
data sheet adp2381 rev. 0 | page 3 of 28 specifications v in = 12 v, t j = ? 40 c to +125 c for min/max specifications, and t a = 25c for typical specification s , unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit pvin pvin voltage range v pvin 4.5 20 v quiescent current i q no s witching 2 2.8 3.5 ma shutdown current i shdn en/ss = gnd 80 130 17 0 a pvin undervoltage lockout threshold pvin rising 4.3 4.5 v pvin falling 3.7 3.9 v fb fb regulation voltage v fb 0c < t j < 85c 0. 594 0. 6 0. 606 v ? 40 c < t j < + 125 c 0. 591 0. 6 0. 609 v fb bias current i fb 0.01 0.1 a error amplifier (ea) transc onductance g m 36 0 500 62 0 s ea source current i source 40 6 0 80 a ea sink current i sink 40 60 80 a i nternal r egulator (vreg) vreg voltage v vreg v pvin = 12 v, i vreg = 50 ma 7.6 8 8 .4 v dropout voltage v pvin = 12 v, i vreg = 50 ma 3 50 mv regulator current l imit 65 100 135 ma sw high - side on resistance 1 v bs t ? v sw = 5 v 44 70 m high - side peak current limit 7.7 9 .6 1 1.5 a negative current - limit threshold voltage 2 20 mv sw minimum on time t min_on 120 170 ns sw min imum off time t min_off 200 300 ns low - side driver (ld) rising time 2 t r c dl = 2 .2 nf ; see figure 17 20 ns falling time 2 t f c dl = 2 .2 nf ; see figure 20 10 ns sourcing resistor 4 6 sinking resistor 2 3.5 bst bootstrap voltage v boot 4.5 5 5.7 v oscillator (rt pin) switching frequency f sw rt pin connected to gnd 21 0 29 0 36 0 khz rt pin open 40 0 55 0 69 0 khz r osc = 100 k 425 500 57 0 khz switching frequ e ncy range f sw 25 0 1400 khz sync synchronization range 25 0 1400 k hz sync minimum pulse width 100 ns sync minimum off time 100 ns sync input high voltage 1.3 v sync input low voltage 0.4 v en/ss enable threshold 0.5 v internal soft start 1 500 clock cycles ss pin pull - up current i ss_up 2.6 3.3 4 a
adp2381 data sheet rev. 0 | page 4 of 28 parameter symbol test conditions/comments min typ max unit power good (pgood) pgood range fb rising threshold 95 % fb falling threshold 90 % pgood deglitch time pgood from low to high 1024 clock cycles pgood from high to low 16 clock cycles pgood leakage current v pgood = 5 v 0. 01 0. 1 a pgood output low voltage i pgood = 1 ma 125 2 00 mv uvlo rising threshold 1.2 1.28 v falling threshold 1.02 1.1 v thermal thermal shutdown threshold 150 c thermal shutdown hysteresis 25 c 1 pin - to - pin measurement. 2 guaranteed by design.
data sheet adp2381 rev. 0 | page 5 of 28 absolute maximum ratings table 2 . parameter rating p vin, pgood ? 0.3 v to + 22 v sw ? 1 v to + 22 v bst v sw + 6 v uvlo, fb , en/ s s, comp, sync, rt ? 0.3 v to +6 v vreg, ld ? 0.3 v to +12 v pgnd to gnd ? 0.3 v to +0.3 v operating junction temperature range ? 40c to +125c storage temperature range ? 65c to +150c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified , all other voltages are refer enced to gnd. thermal i nformation table 3 . thermal resistance package type ja unit 16 - lead tssop_ep 39.48 c/w ja is specified for the worst - case conditions, that is , a devic e soldered in circuit board (4 -l ayer, jedec s tandard board) for surface - mount packages. esd caution
adp2381 data sheet rev. 0 | page 6 of 28 pin configuration and function descripti on figure 3. pin configuration (top view) table 4 . pin function descriptions pin no. mne monic description 1, 2 pvin power input. connect to the input power source and connect a bypass capacitor between this pin and pgnd. 3 uvlo underv oltage lockout pin. an e xternal resistor divider can be used to set the turn - on threshold. 4 pgood power - good output (open drain). a pull - up resistor of 10 k to 100 k is recommended. 5 rt frequency setting. connect a resistor between rt and gnd to program th e switching frequency between 25 0 khz and 1.4 mhz. if the rt pin is connected to gnd, the switching frequency is set to 290 khz. if the rt pin is open, the switching frequency is set to 550 khz. 6 sync synchronization input. connect this pin to an external clock to synchronize th e switching frequency betwee n 25 0 khz and 1.4 mhz (see the oscillator section and the synchronization section for details). 7 en/ss enable pin (en). when this pin voltage falls below 0.5 v, the regulator is disabled. soft start (ss). this pin can also be used to set the s oft s tart time. connect a capacitor from ss to gnd to program the slow soft start time. if this pin is open, the regulator is enabled and uses the internal soft start. 8 comp error amplifier output. connect an rc network from comp to fb. 9 fb feedback voltage sense input . connect to a resistor di vider from v out . 10 gnd analog ground. connect to the ground plane. 11 pgnd power ground. connect to the source of the synchronous n - channel mosfet. 12 vreg internal 8 v regulator output. place a 1 f ceramic capacitor between this pin and gnd . 13 ld low -s ide g ate d river o utput. connect this pin to the gate of the synchronous n - mosfet. 14, 15 sw switch node output . connect this pin to the output inductor. 16 bst supply rail for the high - side gate drive. place a 0.1 f ceramic capacitor between sw and bst. 17 epad the exposed pad should be soldered to an external ground plane underneath the ic for thermal dissipation. top view (not to scale) 1 2 3 4 5 6 7 8 adp2381 16 15 14 13 12 11 10 9 pvin uvlo pgood en/ss sync rt pvin sw sw ld gnd com p fb pgnd vreg bst 10209-003 notes 1. the exposed pad should be soldered to an external ground plane underneath the ic for thermal dissipation.
data sheet adp2381 rev. 0 | page 7 of 28 typical performance characteristics operating conditions: t a = 25 o c, v in = 12 v, v out = 3.3 v, l = 2.2 h, c out = 2 100 f, f sw = 500 khz, unless otherwise noted. figure 4 . efficiency at v in = 12 v, f sw = 500 khz figure 5 . efficiency at v in = 18 v, f sw = 500 khz figure 6. shutdown current vs. v in figure 7 . efficiency at v in = 12 v, f sw = 250 khz figure 8 . efficiency at v in = 5 v, f sw = 500 khz figure 9 . quiescent current vs. v in 100 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 10209-004 v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-2r2m mosfet: fds6298 100 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 10209-005 v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-3r3m mosfet: fds6298 10209-006 90 100 1 10 120 130 140 150 160 4 6 8 10 12 14 16 18 20 shutdown current (a) v in (v) t j = ?40c t j = +25c t j = +125c 100 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 10209-007 v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-4r7m mosfet: fds6298 100 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) output current (a) 10209-008 v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor: 744 333 0100 mosfet: fds6298 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 4 6 8 10 12 14 16 18 20 quiescent current (ma) v in (v) 10209-009 t j = ?40c t j = +25c t j = +125c
adp2381 data sheet rev. 0 | page 8 of 28 figure 10 . pvin uvlo threshold vs. temperature figure 11 . ss pin pull -u p current vs. temperature figure 12 . frequency vs. temperature figure 13 . uvlo pin threshold vs. temperature figure 14 . fb voltage vs. temperature figure 15 . vreg voltage vs. temperature 10209-010 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?40 ?20 0 20 40 60 80 100 120 pvin uvlo threshold (v) tempera ture (c) rising f alling 10209-011 3.30 2.90 ?40 120 ss pull-up current (a) temperature (c) 2.95 3.00 3.05 3.10 3.15 3.20 3.25 ?20 0 20 40 60 80 100 530 520 510 470 480 490 500 ?40 120 frequency (khz) temperature (c) 10209-012 ?20 0 20 40 60 80 100 r osc = 100k? 10209-013 1.00 1.30 ?40 ?20 0 20 40 60 80 100 120 uvlo pin threshold (v) tempera ture (c) 1.05 1.10 1.15 1.20 1.25 rising f alling 606 604 602 594 596 598 600 ?40 120 feedback voltage (mv) temperature (c) 10209-014 ?20 0 20 40 60 80 100 10209-015 8.4 7.6 ?40 120 vreg voltage (v) temperature (c) 7.7 7.8 7.9 8.0 8.1 8.2 8.3 ?20 0 20 40 60 80 100
data sheet adp2381 rev. 0 | page 9 of 28 figure 16 . mosfet r dson vs. temperature figure 17 . low - side driver rising edge waveform, c dl = 2.2 nf figure 18 . working mode waveform figure 19 . current - limit threshold vs. temperature figure 20 . low - side driver falling edge waveform, c dl = 2.2 nf figure 21 . soft start with full load 70 60 20 30 40 50 ?40 120 mosfet r dson (m?) temperature (c) 10209-016 ?20 0 20 40 60 80 100 10209-017 ch2 5.00v ch1 5.00v m20.0ns a ch2 3.70v 1 2 t 46.60% sw ld 10209-018 ch2 10v ch4 2a ? ch1 10mv b w m2.00s a ch2 6.00v 4 2 1 t 50.00% v out (ac) i l sw 11.0 10.5 10.0 8.0 8.5 9.0 9.5 ?40 120 peak current limit threshold (a) temperature (c) 10209-019 ?20 0 20 40 60 80 100 10209-020 ch2 5.00v ch1 5.00v m20.0ns a ch2 3.70v 1 2 t 43.80% sw ld 10209-021 ch2 5.00v ch4 5.00a ? ch1 2.00v ch3 5.00v m2.00ms a ch2 5.80v 1 3 2 4 t 50.00% en/ss pgood v out i out b w
adp2381 data sheet rev. 0 | page 10 of 28 figure 22 . precharged output figure 23 . load transient response, 1 a to 5 a figure 24 . output short entry figure 25 . external synchronization figure 26 . line transient response, v in from 10 v to 1 6 v, i out = 6 a figure 27 . output short recovery 10209-022 ch2 5.00v ch4 5.00a ? ch1 2.00v ch3 5.00v m2.00ms a ch2 2.00v 1 3 2 4 t 49.60% en/ss pgood v out i l b w 10209-023 ch1 100mv m200s a ch4 2.52 a 1 4 t 70.20% ch4 2.00a ? v out (ac) i out b w 10209-024 ch2 10.0v ch4 5.00a ? ch1 2.00v m10.00ms a ch1 1.96v 1 2 4 t 30.40% v out sw i l b w 10209-025 ch2 10.0v m1.00s a ch2 7.00v 3 2 t 50.00% ch3 5.00v sync sw b w 10209-026 ch2 10.0v ch1 20.0mv ch3 5.00v m1.00ms a ch3 13.5v 1 2 3 t 20.20% v out (ac) sw v in i l b w b w b w 10209-027 ch2 10.0v ch4 5.00a ? ch1 2.00v m10.00ms a ch1 1.96v 1 2 4 t 60.40% v out sw i l b w
data sheet adp2381 rev. 0 | page 11 of 28 figure 28 . load current vs . ambient temperature, v in = 12 v, f sw = 500 khz figure 29 . load current vs . ambient temperature, v in = 12 v, f sw = 250 khz 7 0 1 2 3 4 5 6 25 40 55 70 85 100 load current (a) ambient temperature (c) 10209-028 v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 7 0 1 2 3 4 5 6 25 40 55 70 85 100 load current (a) ambient temperature (c) 10209-029 v out = 1v v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v
adp2381 data sheet rev. 0 | page 12 of 28 functional block diagram figure 30 . functional block diagram adp2381 oscillator rt sync uvlo clk slope ramp control logic and mosfet driver with anticross protection pgood gnd uvlo slope ramp ld pgnd + ? + 0.6v i ss en/ss fb amp comp 0.7v 0.54v 1.2v ovp clk + ? + ? + ? i max hiccup mode cmp ocp + ? + ? sw nfet bst driver vreg driver boost regulator deglitch bias and driver regulator + ? a cs pvin vreg 320k? 125k? pvin 10209-030 neg a tive current limit cm p + ?
data sheet adp2381 rev. 0 | page 13 of 28 theory of operation the adp2381 is a synchronous , step - down, dc - to - dc regulator. it uses current - mode architecture with an integrated high - side power switch and a low - side driver. it targets high performance applications that require high efficiency and design flexibility. the adp2381 can operate with an input voltage from 4.5 v to 20 v and regulate the output voltage down to 0. 6 v. additional features for design flexibility include programmable switching frequency, soft start, external compensation , and power - good pin. control scheme the adp2381 uses fixed frequency, peak current - mode pwm control architecture. at the start of each oscillator cycle, the high - side n - mosfet is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current thresh - old that turns off the high - side n - mosfet and turn s on the low - side n - mosfet. this puts a negative voltage across the inductor, causing the inductor current to decrease. the low - side n - mosfet stays on for the rest of the cycle. internal regulator ( vreg) the internal regulator provides a stable supply for the internal circuits and pr ovides bias voltage for the low - side gate driver. placing a 1 f ceramic capacitor between vreg and gnd is recommended. the internal regulator also includes a current - limit circuit to protect the circuit if the maximum external load is added. bootstrap circuitry the adp2381 has integrated the boot regulator to provide the gate drive voltage for the high - side n - mosfet. it generates a 5 v bootstrap voltage between bst and sw by differential sensing. it is recommended to place a 0.1 f, x7r or x5r ceramic capacitor between the bst pin and the sw pin. low- side driver the ld pin provides the gate driver for the low - side n - channel mosfet . internal circuitry monitors the external mosfet to ensure break - before - make switching to prevent cross conduction. oscillator the adp2381 switching frequency is controlled by the rt pin. if the rt pin is connected to gnd, the switching frequency is set to 29 0 khz. if the rt pin is open, the swi tching frequency is set to 55 0 khz. a resistor connected from rt to gnd can program the switching frequency according to the following equation: 15]k[ 600,57 ] khz [ + = osc sw r f a 100 k resistor sets the frequency to 500 khz , and a 215 k resistor sets the frequency to 250 khz. figure 31 shows the typical relationship between f sw and r osc . figure 31 . switching frequency vs. r osc synchronization to synchronize the adp2381 , connect an external clock to the sync pin. the frequency of the external clock can be in the range of 2 50 khz to 1.4 mhz. during synchronization, the switching risi ng edge runs 180 out of phase with the external clock rising edge. when the adp2381 is being synchronized , connect a resistor from the rt pin to gnd to program the internal oscillator to run at 90% to 110% of the external synchronization clock. enable and soft star t when the voltage of the en/ss pin exceeds 0.5 v, t h e adp2381 starts operation. the adp2381 has an internal digital soft start . the internal soft start time can be calculated by using the following equation: )ms( ] khz [ 1500 _ sw int ss f t = a s low soft start time can be programmed by the en/ss pin. place a capacitor between the en/ss pin and gnd. an inter nal current charge s this capacitor to establish the soft start ramp. the soft start time can be calculated by using the following equation: upss ss ext ss i c t _ _ v6.0 = w here : c ss is the soft start capacitance . i ss_up is the soft start pull - up current (3.3 a) . the internal error amplifier includes three positive inputs: the internal reference voltage, the internal digital soft start voltage , and the en/ss voltage. the error amplifier regulates the fb voltage to the lowest of the three voltages . 1400 1200 1000 800 600 400 200 0 20 60 100 140 180 220 260 300 switching frequency (khz) r osc n? 10209-031
adp2381 data sheet rev. 0 | page 14 of 28 if the output voltage is charged prior to turn - on, the adp2381 prevents the low - side mosfet from turning on, which discharge s the output voltage until the soft start voltage exceed s the voltage on the fb pin. when the regulator is disabled or a current fault happens, the soft start capacitor is discharged , and the internal digital soft start is reset to 0 v. power good the p ower - good (pgood) pin is an active high, open -d rain output that requires a pull - up resistor . a logic high indicates that the vo ltage at the fb pin (and, therefore, the output voltage) is above 95 % of the reference voltage and there is a 1024 cycle waiting period before pgood is pulled high. a logic low indicates that the voltage at the fb pin is below 90 % of the reference voltage and there is a 16 - cycle waiting period before pgood is pulled low. peak cu rrent limit and shor t- circuit protection the adp2381 has a peak current - limit protection circuit to prevent current runaway. during soft start, the adp2381 uses frequency foldback to prevent output current runaway. the switching frequency is reduced according to the voltage on the fb pin, which allows more time for the inductor to discharge. the correlation between the switching frequency and fb pin voltage is shown in table 5 . table 5 . switching frequency and fb pin voltage fb pin voltage switching frequency v fb 0.4 v f sw 0.4 v > v fb 0.2 v f sw /2 v fb < 0.2 v f sw /4 for heavy load protection, the adp2381 uses hiccup mode for overcurrent protection. when the inductor peak current reaches th e current - limit value, the high - side mosfet turns off and the low - side driver turns on until the next cycle , while the over cur rent counter increments. if the over curren t counter reaches 10, or the fb pin voltage falls to 0. 4 v after the soft start, the regulat or enters hiccup mode. the high - side mosfet and low - side mosfet are both turned off. the regulator remains in this mode for 4096 clock cycles and then attempts to restart. if the current limit fault is cleared, the regulator resumes normal operation. otherwise, it reenters hiccup mode. the adp2381 also provides a sink current limit to prevent the low - side mosfet from sinking a lot of current from the load . when the voltage across the low - side mosfet exceeds the sink current - limit threshold, which is typical ly 20 mv, the low - side mosfet turns off immediately for th e rest of this cycle. both high - side and low - side mosfe ts turn off until the next clock cycle . in some cases, the input voltage (pvin) ramp rate is too slow or the output capacitor is too large to support the setting regula tion voltage during the soft start , causing the regulator to enter hiccup mode. to avoid such cases, use a resistor divider at the uvlo pin to program the uvlo input voltage, or use a longer soft start time. over voltage protection ( ovp) the adp2381 provides an overvoltage protection feature to protect the system against an output short ing to a higher voltage supply or a strong load transient occurring . if the feed back voltage increases to 0.7 v, the internal high - side mosfet and low - side driver are turned off until the voltage at fb decreases to 0.63 v. at that time , the adp2381 resumes normal operation. under voltage lockout (uvl o) the uvlo pin enable threshold is 1.2 v with 100 mv hysteresis. the adp2381 has an internal voltage divider consisting of two resistors from pvin to gnd, 320 k for the high - side resistor and 125 k for the low - side resistor. an e xternal resistor divider from pvin to gnd can be used to override the internal resistor divider. thermal shutdown in the event that the adp2381 junction temperatures rise above 150 c, the thermal shutdown circuit turns off the regulator. extreme junction temperatures can be the result of high current operation, poor circuit board design, and/o r high ambient temperature. a 25 c hysteresis is included so that when thermal shutdown occurs, the adp2381 do es not return to oper ation until the on - chip tempera ture drops below 12 5 c. upon recovery, soft start is initiated prior to normal operation.
data sheet adp2381 rev. 0 | page 15 of 28 applications information input capaci tor selection the input decoupling capacitor is used to attenuate high frequency noise on the input. this capacitor should be a ceramic capacitor in the range of 10 f to 47 f. it should be placed close to the pvin pin. the loop compose d by this input capacitor, high - side nfet , and low - side nfet must be kept as small as possible. the voltage rating of the input capacitor must be greater than the maximum input voltage. the rms current rating of the input capacitor should be larger than the following equa tion: )1( _ ddii out rms c in ?= output voltage setti ng the output voltage of adp2381 can be set by an external resistive divider using the following equation: ? ? ? ? ? ? ? ? += bot top out r r v 16.0 to limit output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximum), ensure that r bot is less than 30 k?. table 6 gives the recommended resistor divider values for various output voltage options. table 6. resistor divider for different output voltage s v out (v) r top , 1% ( k ) r bot , 1% ( k ) 1.0 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 47.5 15 3.3 10 2.21 5.0 22 3 voltage conversion l imitations the minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. the minimum on time of the adp2381 is typically 1 2 0 ns. the minimum output voltage at a given input voltage and frequency can be calculated using the following equation: v out_min = v in t min_on f sw C ( r dson_hs C r dson_ls ) i out_min t min_on f sw C ( r dson_ls + r l ) i out_min (1) where: v out_min is the minimum output voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson_hs is the high - side mosfet on resistance. r dson_ls is the low - side mosfet on resistance. i out_min is the minimum output current. r l is the series resistance of the output inductor. the maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maximum duty cycle. the minimum off time is typically 20 0 ns , and the maximum duty cycle of the adp2381 is typically 90%. the maximum output voltage limited by the minimum off time at a given input voltage and frequency can be calculated using the following equation: v out_max = v in (1 C t min_off f sw ) C ( r dson_hs C r dson_ls ) i out_max (1 C t mi n_off f sw ) C ( r dson_ls + r l ) i out_max (2) where: v out_max is the maximum output voltage. t min_off is the minimum off time. i out_max is the maximum output current. the maximum output voltage , limited by the maximum duty cycle at a given input voltage , c an be calculated by using the following equation: v out_max = d max v in (3) where d max is the maximum duty. as equation 1 to equation 3 show, reducing the switching frequency alleviates the minimum on time and minimum off time limitation. inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. using a small inductor leads to a faster transient response , but it degrades efficiency due to larger inductor ripple current , whereas using a large inductor value leads to smaller ripple current and better efficiency , but it results in a slower transi ent response. as a guideline, the inductor ripple current, i l , is typically set to 1/3 of the maximum load current. the induct or can be calculated using the following equation: ( ) d fi vv l sw l out in ? ? = where: v in is the input voltage. v out is the output voltage. i l is the inductor current ripple. f sw is the switching frequency. d is the duty cycle. in out v v d = the adp2381 uses adaptive slope compensation in the current loop to prevent sub harmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value.
adp2381 data sheet rev. 0 | page 16 of 28 for a d uty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: sw out f d v ? 2 )1( the inductor peak current is calculated using the following equation: 2 l out peak i ii ? += the saturation current of the inducto r must be larger than the peak inductor current. for the ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor should be higher than the current - limit thresh old of the switch to prevent the inductor f rom becoming saturated . the rms current of the inductor can be calculated by 12 2 2 l out rms i ii ? += shielded f errite core materials are recommended for low core loss and low emi. table 7 lists some recommended inductors. table 7 . recommended inductors vendor part no. value i sat a i rms a dcr m toko fdve0630 - r47m 0.47 15.6 14.1 3.7 fdve0630 - r75m 0.75 10.9 10.7 6.2 fdve0630 - 1r0m 1.0 9.5 9.5 8.5 fdve1040 - 1r5m 1.5 13.7 14.6 4.6 fdve1040 - 2r2m 2.2 11.4 11.6 6.8 fdve1040 - 3r3m 3.3 9.8 9.0 10.1 fdve1040 - 4r7m 4.7 8.2 8.0 13.8 vishay ihlp3232dz - r47m - 11 0.47 14 25 2.38 ihlp3232dz - r68m -11 0.68 14.5 22.2 3.22 ihlp3232dz - 1r0m -11 1.0 12 18.2 4.63 ihlp4040dz - 1r5m -01 1.5 27.5 15 5.8 ihlp4040dz - 2r2m -01 2.2 25.6 12 9 ihlp4040dz - 3r3m - 01 3.3 18.6 10 14.4 ihlp4040dz - 4r7m -01 4.7 17 9.5 16.5 wurth elektronik 744 325 120 1.2 25 20 1.8 744 325 180 1.8 18 16 3.5 744 325 240 2.4 17 14 4.75 744 325 330 3.3 15 12 5.9 744 325 420 4.2 14 11 7.1
data sheet adp2381 rev. 0 | page 17 of 28 output capacitor sel ection the output capacitor selection affects both the output ripple voltage and the loop dynamics of the regulator. during a load step transient on the output, for example , when the load is suddenly increased, the output capacitor supplies the load until the co ntrol loop has a chance to ramp up the inductor current, which causes the output to under shoot. the output capacitance required to satisfy the voltage droop requirement can be calculated using the following equation: ( ) uv out out in step uv uv out vvv lik c _ 2 _ 2 ?? ? = w here: k uv is a factor typically of 2. i step is the load step. v out_uv is the allowable undershoot on the output voltage. another case occurs when a load is suddenly removed from the output . the energy stored in the inductor rush es into the capacitor, which cause s the output to overshoot. the output capacitance required to meet the overshoot requirement can be calculated using the following equation: ( ) 2 2 _ 2 _ out ovout out step ov ovout v vv lik c ? ?+ ? = where: k ov is a factor typically of 2. v out_ov is the allowable undershoot on the output voltage. the output ripple is determined by the esr and the capaci - tance. use the following equation to select a capacitor that can meet the output ripple requirements: ripple out sw l ripple out vf i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ w here: v out_ ripple is the allowable output ripple voltage. r esr is the equivalent series resistance of the output capacitor . select the largest output capacitance given by c out_uv , c out_ov , and c out_ ripple to meet both load transient and output ripple performance. the selected output capacitor voltage rating should be greater than the output voltage. the rms current rating of the output capacitor should be larger than the following equation: 12 _ l rms c i i out ? = low- side power device se lection the adp2381 has an integrated low - side mosfet driver that drives the low - side nfet. the selection of the low - side nfet affects the dc - to - dc regulator performance. the selected mosfet must meet the following requiremen ts: ? drain -s ource voltage (v ds ) must be higher than 1.2 v in . ? drain current (i d ) must be greater than 1.2 i limit_max , which is the selected maximum current - limit threshold. ? the adp2381 low - side gate drive vo ltage is 8 v. make sure that the selected mosfet can fully turn on at 8 v. total gate charge ( q g at 8 v) must be less than 50 nc. lower q g characteristics constitute higher efficiency. ? the low - side mosfet carries the inductor current when the high - side mosfet is turned off. for low duty cycle application , the low - side mosfet carries the output current during most of the period. to achieve higher efficiency, it is important to select a low on -resistance mosfet. the power conduction loss of the low - side mo sfet can be calculated by using the following equation : p fet_low = i out 2 r dson (1 C d) where r dson is the on resistance of the low - side mosfet. ? make sure that the mosfet can handle the thermal dissipation due to the power loss. some recommended mosfets are listed in table 8 . table 8 . recommended m os fets vendor part no. v ds (v) i d (a) r dson ( m ) q g (nc) fairchild fds6298 30 13 12 10 fairchild FDS8880 30 10.7 12 12 fairchild fdm7578 25 14 8 8 vishay sia430dj 20 10.8 18.5 5.3 aos aon7402 30 39 15 7.1 aos ao4884l 40 10 16 13.6
adp2381 data sheet rev. 0 | page 18 of 28 programming input vo ltage uvlo the internal voltage divider fro m pvin to gnd sets the default start/stop value s of the input voltage to achieve undervoltage lockout (uvlo) performance. the default rising/falling threshold of pvin and uvlo are listed in table 9 . these default values can be replaced by using an external voltage divider to achieve a more accurate externally adjustable uvlo , as shown in figure 32 . lower values of the external resistors are recommended to obtain a high accuracy uvlo threshold because the values of the internal 320 k? and 125 k? resistors may vary by as much as 20%. table 9. default rising / falling voltage threshold pin rising threshold (v) falling threshold (v) pvin 4.28 3.92 uvlo 1.2 1.1 figure 32 . external programmable uvlo a 1 k? resistor for r2 is an appropriate choice. use the following e quation to obtain the value of r1 for a chosen input voltage rising threshold: ( ) v2.1 v2.1 _ r2 v r1 rising in ? = w here v in_rising is the rising threshold of v in . the falling threshold of vin can be determined by the following equation: v1.1 2 v1.1 _ + = w here v in_falling is the falling threshold of v in . compensation design the adp2381 uses a peak current - mode control architecture for excellent load and line trans ient response. for peak current - mode control, the power stage can be simplified as a voltage controlled current source , supplying current to the output capacitor and load resistor. it consists of one domain pole and one zero contributed by the output capacitor esr. the control t o output transfer function is given by the following equation: p vi comp out vd f s f s ra s v sv sg + ? ? ? ? ? ? ? ? + = = 2 1 2 1 )( )( )( out esr cr f = 2 1 out esr p crr f + = )(2 1 w here: a vi = 8.7 a/v . r is the load resistance . c out is the output capacitance . r esr is the equivalent series resistance of the output capacitor . the external voltage loop is compensated by a transconduct - ance amplifier with a simple external rc network placed either between comp and gnd or between comp and fb, as shown in figure 33 and figure 34 , respectively . compensation network between comp and gnd figure 33 shows the simplified peak current mode control small signal circuit with a compensation network placed between comp and gnd. figure 33 . small s ignal c ircuit with compensation n etwork b etween comp and gnd the r c and c c compensation components contribute a zero , and the optional c cp and r c contribute an optional pole. the close d- loop transfer function is as follows : )( 1 1 )( sg s cc ccr s scr cc g rr r st vd cpc cpcc cc cpc m top bot bot v ? ? ? ? ? ? ? ? + + + + ? + = use t he following design guidelines to select the r c , c c , and c cp compensation components : ? determine the cross frequency , f c . generally, fc is between f sw /12 and f sw /6. ? r c can be calculated by vi m ref c out out c agv fcv r = 2 w here: v ref = 0.6 v. g m = 500 s. ? place the compensation zero at the domain pole , f p . c c can be determined by: c out esr c r crr c + = )( pvin vin r1 r2 uvlo n? n? adp2381 10209-032 r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 10209-033 adp2381 gnd comp fb
data sheet adp2381 rev. 0 | page 19 of 28 ? c cp is optional , and it can be used to cancel the zero caused by the esr of the output capacitors. c out esr cp r cr c = compensation network between comp and fb the compensation rc network can also be placed between comp and fb , as shown in figure 34. figure 34 . small s ignal c ircuit with compensation n etwork b etween comp and fb when connecting the compensation network as shown in figure 34 , it should have the same pole and z ero as in figure 33 to maintain the same compensation performance. assuming that the compensation networks of fig ure 33 and figure 34 have the same pole and zero, )1 )( // )( ( ) ( )( )1 )( // ( _ _ __ _ _ ___ ___ _ _ __ 0 m bot top ea c ea cp ea c ea c ea c ea cp 0 ccccp 0 0 m bot top ea cp ea c ea c ea cp ea c ea c 0 cpcc 0 m ea c ea cp ea c ea ccc rgrrcc crccr crccr rgrrccr ccrrccrr g cc crcr + + + ++ =++ + + = + ? = where: r 0 is the equivalent output impedance of the trans - conductance amplifier, 40 m?. bot top bot top bot top rr rr rr + = // solve the preceding equations to obtain : ) )( ( ) )( ( _ _ _ _ arcrb ccrr c c crb r arcrb ccrr gbc 0 cc cpcc 0 ea cp ea c cc ea c 0 cc cpcc 0 m ea c + + = + = + + ?= where: )(1 )( )1 )( // ( 0 m ccp 0 0 m bot top rag ccr b rgrra ++ + = + = adi sim p ower design tool the adp2381 is supported by the adisimpower? design tool set. adisimpower is a collection of tools that produce complete power designs that are optimized for a specific design goal. the tools enable the user to gener ate a full schematic and bill of materials and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count, while taking into consideration the operating conditions and limitations of the ic and all real e xternal components. for more information about the adisimpower design tools, visit www.analog.com/adisimpower . the tool set is available from this website, and users can request an unpopulated board. r esr r + ? g m c out r top r bot ? + a vi v out v comp v out 10209-034 adp2381 gnd comp fb c cp_ea r c_ea c c_ea
adp2381 data sheet rev. 0 | page 20 of 28 design example this section provides the procedures of selecting the external components based on the example specifications listed in table 10. the schematic of this design example is shown in figure 36. table 10. step-down dc-to-dc regulator requirements parameter specification input voltage v in = 12.0 v 10% output voltage v out = 3.3 v output current i out = 6 a output voltage ripple ?v out_ripple = 33 mv load transient 5%, 1 a to 5 a, 2 a/s switching frequency f sw = 500 khz output voltage setting choose a 10 k resistor as the top feedback resistor (r top ) and calculate the bottom feedback resistor (r bot ) by using the following equation: ? ? ? ? ? ? ? ? ? ?? 6.0 6.0 out top bot v rr to set the output voltage to 3.3 v, the resistors values are r top = 10 k, r bot = 2.21 k. frequency setting connect a 100 k resistor from rt pin to gnd to set the switching frequency at 500 khz. inductor selection the peak-to-peak inductor ripple current, i l , is set to 30% of the maximum output current. use the following equation to estimate the inductor value: sw l out in fi dvv l ?? ?? ? ) ( where: v in = 12 v. v out = 3.3 v. d = v out /v in = 0.275. i l = 1.8a. f sw = 500 khz. this results in l = 2.659 h. choose the standard inductor value of 2.2 h. the peak-to-peak inductor ripple current can be calculated by the following equation: ? ? sw out in l fl dvv i ? ?? ?? this results in i l = 2.18 a. the peak inductor current can be calculated using the following equation: 2 l out peak i ii ? ?? this results in i peak = 7.09 a. the rms current flowing through the inductor can be calculated by the following equation: 12 2 2 l out rms i ii ? ?? this results in i rms = 6.03 a. according to the calculated rms and peak inductor current values, select an inductor with a minimum rms current rating of 6.03 a and a minimum saturation current rating of 7.09 a. to protect the inductor from reaching its saturation limit, the inductor should be rated for at least 9.6 a saturation current for reliable operation. based on these requirements, select a 2.2 h inductor, such as the fdve1040-2r2m from toko, which has 6.8 m dcr and 11.4 a saturation current. output capacitor selection the output capacitor is required to meet both the output voltage ripple requirement and the load transient response. to meet the output voltage ripple requirement, use the following equation to calculate the esr and capacitance of the output capacitor: ripple out sw l ripple out vf i c _ _ 8 ??? ? ? l ripple out esr i v r ? ? ? _ this results in c out_ripple = 16.5 f and r esr = 15.1 m. to meet the 5% overshoot and undershoot transient requirements, use the following equations to calculate the capacitance: uvout out in step uv uvout out ovout out step ov ovout vvv lik c v vv lik c _ 2 _ 2 2 _ 2 _ ) (2 ) ( ???? ??? ? ? ?? ??? ? where: k ov = k uv = 2, the coefficients for estimation purposes. i step = 4 a, the load transient step. v out_ov = 5%v out , the overshoot voltage. v out_uv = 5%v out , the undershoot voltage. this results in c out_ov = 63.1 f and c out_uv = 24.5 f. according to the preceding calculation, the output capacitance must be larger than 63 f, and the esr of the output capacitor must be smaller than 15 m. it is recommended that one 100 f, x5r, 6.3 v ceramic capacitor and one 47 f, x5r, 6.3 v ceramic capacitor be used, such as the grm32er60j107me20 and grm32er60j476me20 from murata with an esr = 2 m.
data sheet adp2381 rev. 0 | page 21 of 28 low- side mosfet selectio n a low r dson n-c hannel mosfet is selected as a high efficiency solution. the breakdown voltage of the mosfet must be higher than 1.2 v in , and the drain current must be larger than 1.2 i limit . it is recommended that a 30 v, n -c hannel mosfet, such as the fds 6298 from fairchild, be used. the r dson of the fds 6298 at a 4.5 v driver voltage is 9.4 m?, and the total gate charge at 5 v is 10 nc. compensation compone nts for a better load transient and stability performance, set the cross frequency , f c , at f sw /10. in this case, f c = 1/500 khz = 50 khz. ) )( ( ) )( ( _ _ _ 0 _ arcrb ccrr c c crb r arcrb ccrr gbc 0 cc cpcc 0 ea cp ea c cc ea c 0 cc cpcc m ea c + + = + = + + ?= where: k3.37 /7.8 s 500v6.0 khz 50 f 943.32 2 = = = va v agv fcv r vi m ref c out out c nf 39.1 k3.37 f 94)002.0a6/v3.3( )( = ?+ = + = c out esr c r crr c pf 04.5 k3.37 f 94002.0 = ? = = c out esr cp r cr c ( ) ( ) 7 1062.3m40 s 5001 k21.2k10 k2.21k10 1 =+ + =+ + = 0 m bot top bot top rg rr rr a 6 7 1046.1 )m401062.3( s 5001 ) nf 39.1 pf 04.5(m40 )(1 )( ? = ++ + = ++ + = 0 m ccp 0 rag ccr b this results in r c_ea = 73.3 k? . c c_ea = 727.6 pf . c cp_ea = 2.56 pf . choose the standard values for r c_ea = 73.2 k?, c c_ea = 820 p f, and c cp_ea = 2.2 p f. figure 35 shows the bode plot at 6 a. the cross frequency is khz , and the phase margin is 61 . figure 35 . bode plot at 6 a soft start time prog ram the soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting the inrush current. set the soft start time to 4 ms. nf 22 v6.0 a 3.3ms4 6.0 _ _ = = = upss ext ss ss it c choose a standard component value , c ss = 22 n f. input capacitor sele ction a minimum 10 f ceramic capacitor is required to be placed near the pvin pin. in this application, one 10 f, x5r, 25 v ceramic capacitor is recommended. schematic of design example see figure 36 for a schematic of the design example. 60 48 36 24 12 0 ?60 ?48 ?36 ?24 ?12 180 144 108 72 36 0 ?180 ?144 ?108 ?72 ?36 1k 10k 100k 1m magnitude (db) phase (db) freequency (hz) 10209-035
adp2381 data sheet rev. 0 | page 22 of 28 figure 36 . schematic of d esign e xample adp2381 10209-036 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r top 10k? 1% r bot 2.21k? 1% c ss 22nf r osc 100k? c in 10f 25v c out1 100f 6.3v c out2 47f 6.3v v out = 3.3v c bst 0.1f c vreg 1f l1 2.2h v in = 12v c c_ea 820pf c cp_ea 2.2pf r c_ea 73.2k? m1 fds6298
data sheet adp2381 rev. 0 | page 23 of 28 external components recommendation table 11 . recommended external components for typical applications with compensation network between comp and gnd, 6 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k) r bot (k) r c (k) c c (pf) c cp (pf) 250 12 1 2.2 680 + 470 10 15 68 2700 150 12 1.2 2.2 680 + 2 100 10 10 56 2700 130 12 1.5 3.3 680 + 2 100 15 10 71.5 2700 100 12 1.8 3.3 680 20 10 71.5 2700 91 12 2.5 4.7 470 47.5 15 69.8 2700 62 12 3.3 4.7 3 100 10 2.21 36 2700 10 12 5 6.8 2 100 22 3 36 2700 6.8 5 1 1.5 680 + 2 100 10 15 47 2700 150 5 1.2 2.2 680 + 2 100 10 10 56 2700 130 5 1.5 2.2 680 15 10 59 2700 100 5 1.8 2.2 470 20 10 47 2700 91 5 2.5 3.3 3 100 47.5 15 28 2700 10 5 3.3 2.2 3 100 10 2.21 36 2700 10 500 12 1.2 1 470 10 10 62 1500 68 12 1.5 1.5 470 15 10 82 1500 56 12 1.8 1.5 3 100 20 10 39 1500 10 12 2.5 2.2 3 100 47.5 15 56 1500 6.8 12 3.3 2.2 2 100 10 2.21 47 1500 4.7 12 5 3.3 100 22 3 36 1500 3.3 5 1 1 680 10 15 75 1500 82 5 1.2 1 470 10 10 62 1500 68 5 1.5 1 3 100 15 10 33 1500 10 5 1.8 1 2 100 20 10 25.5 1500 8.2 5 2.5 1.5 2 100 47.5 15 36 1500 6.8 5 3.3 1 100 + 47 10 2.21 36 1500 4.7 1000 12 1.8 1 2 100 20 10 51 680 4.7 12 2.5 1 100 47.5 15 36 680 3.3 12 3.3 1.5 100 10 2.21 47 680 2.2 12 5 1.5 100 22 3 73.2 680 1.8 5 1 0.47 3 100 10 15 43 680 8.2 5 1.2 0.47 2 100 10 10 34.8 680 6.8 5 1.5 0.68 2 100 15 10 43 680 6.8 5 1.8 0.68 100 + 47 20 10 39 680 4.7 5 2.5 0.68 100 47.5 15 36 680 3.3 5 3.3 0.68 100 10 2.21 47 680 2.2 1 680 f: 4 v, sanyo 4tpf680m; 470 f: 6.3 v, sanyo 6tpf470m; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20.
adp2381 data sheet rev. 0 | page 24 of 28 table 12 . recommended external components for typical applications with compensation network between comp and fb, 6 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k) r bot (k) r c_ea (k) c c_ea (pf) c cp_ea (pf) 250 12 1 2.2 680 + 470 10 15 270 750 39 12 1.2 2.2 680 + 2 100 10 10 200 820 39 12 1.5 3.3 680 + 2 100 15 10 287 680 22 12 1.8 3.3 680 20 10 316 680 22 12 2.5 4.7 470 47.5 15 470 470 10 12 3.3 4.7 3 100 10 2.21 71.5 1500 4.7 12 5 6.8 2 100 22 3 86.6 1200 2.2 5 1 1.5 680 + 2 100 10 15 191 750 39 5 1.2 2.2 680 + 2 100 10 10 200 820 39 5 1.5 2.2 680 15 10 240 680 22 5 1.8 2.2 470 20 10 220 680 22 5 2.5 3.3 3 100 47.5 15 187 390 2.2 5 3.3 2.2 3 100 10 2.21 71.5 1500 4.7 500 12 1.2 1 470 10 10 220 390 22 12 1.5 1.5 470 15 10 330 390 15 12 1.8 1.5 3 100 20 10 169 330 2.2 12 2.5 2.2 3 100 47.5 15 360 220 1 12 3.3 2.2 2 100 10 2.21 93.1 680 2.2 12 5 3.3 100 22 3 86.6 620 1.5 5 1 1 680 10 15 330 390 22 5 1.2 1 470 10 10 220 390 22 5 1.5 1 3 100 15 10 130 330 2.2 5 1.8 1 2 100 20 10 100 330 2.2 5 2.5 1.5 2 100 47.5 15 220 220 1 5 3.3 1 100 + 47 10 2.21 71.5 680 2.2 1000 12 1.8 1 2 100 20 10 232 160 1 12 2.5 1 100 47.5 15 240 100 1 12 3.3 1.5 100 10 2.21 93.1 390 1 12 5 1.5 100 22 3 169 330 1 5 1 0.47 3 100 10 15 178 180 2.2 5 1.2 0.47 2 100 10 10 120 220 2.2 5 1.5 0.68 2 100 15 10 178 180 1 5 1.8 0.68 100 + 47 20 10 169 160 1 5 2.5 0.68 100 47.5 15 240 100 1 5 3.3 0.68 100 10 2.21 93.1 390 1 1 680 f: 4v, sanyo 4tpf680m; 470 f: 6.3 v, sanyo 6tpf470m; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20.
data sheet adp2381 rev. 0 | page 25 of 28 circuit board layout recommendations good circuit board layout is essential for obtaining the best performance from the adp2381 . poor print ed circuit board (pcb) layout degrades the output regulation as well as the electromag netic interface (emi) and electromagnetic compatibility (emc) performance. figure 38 show s a pcb layout example . for optimum layout, use the following guidelines: ? use separate analog ground an d power ground planes. connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. in addition, connect the ground reference of power components, such as input and output capacitors and a low - sid e mosfet, to power ground. connect both ground planes to the exposed pad of the adp2381 . ? place the input capacitor, inductor, low - side mosfet, output capacitor as close to the ic as possible and use short trace s. ? ensure that the high current loop traces are as short and as wide as possible. make the high current path from the input capacitor through the inductor, the output capacitor , and the power ground plane back to the input capacitor as short as possible. to accomplish this, ensure that the input and output capacitors share a common power ground plane. in addition, ensure that the high current path from the power ground plane through the external mosfet, inductor , and o utput capacitor back to the power ground plane is as short as possible by tying the mosfet source node to the pgnd plane as close as possible to the input and output capacitors. ? make the low - side driver path from the ld pin of the adp2381 to the external mosfet gate node and back to the pgnd pin of the adp2381 as short as possible , and use a wide trace for better noise immunity. ? connect the exposed pad of the adp2381 to a large copper plane to maximize its power dissipation capability for better thermal dissipation. ? place the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. try to minimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. to further reduce noise pickup, place an analog ground plane on either side of the fb trace and ensure that the trace is as short as possible to reduce parasitic capacitance pickup. figure 37 . high current path in the pcb circuit 10209-037 adp2381 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r osc r top r bot c ss c in c out v out c bst c vreg l v in c c_ea c cp_ea r c_ea fet
adp2381 data sheet rev. 0 | page 26 of 28 figure 38. recommended pcb layout pvin pvin uvlo pgood rt sync en/ss comp bst sw sw ld vreg pgnd gnd fb sw pull up power ground plane vout pvin input bulk cap input bypass cap analog ground plane r osc c ss inductor low-side mosfet output capacitor r bot r top r c_ea c cp_ea c c_ea c vreg c bst bottom layer trace via copper plane 10209-038
data sheet adp2381 rev. 0 | page 27 of 28 typical application circuits figure 39 . compensation network between comp and gnd, v in = 12 v, v out = 1.2 v, i out = 6 a, f sw = 500 khz figure 40 . programming input voltage uvlo rising threshold at 10 v, v in = 12 v, v out = 1.8 v, i out = 6 a, f sw = 500 khz figure 41 . using internal soft start , programming switching frequency at 600 khz, v in = 12 v, v out = 5 v, i out = 6 a, f sw = 600 khz 10209-039 adp2381 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r top 10k? 1% r bot 10k? 1% c ss 22nf c in 10f 25v c out 470f 6.3v v out = 1.2v c bst 0.1f c vreg 1f l1 1h v in = 12v c cp 68pf c c 1.5nf r c 62k? m1 fds6298 r osc 100k? 10209-040 adp2381 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r top 20k? 1% r bot 10k? 1% c ss 22nf c in 10f 25v c out1 100f 6.3v c out2 100f 6.3v c out3 100f 6.3v v out = 1.8v c bst 0.1f c vreg 1f l1 1.5h v in = 12v c c_ea 330pf c cp_ea 2.2pf r c_ea 169k? m1 fds6298 r1 7.32k? 1% r2 1k? 1% r osc 100k? 10209-041 adp2381 1 pvin pvin uvlo pgood rt sync en/ss com p bst sw sw ld vreg pgnd gnd fb 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r osc 82k? r top 22k? 1% r sot 3k? 1% c in 10f 25v c out 100f 6.3v v out = 5v c bst 0.1f c vreg 1f l1 3.3h v in = 12v c c_ea 620pf c cp_ea 1.5pf r c_ea 86.6k? m1 fds6298
adp2381 data sheet rev. 0 | page 28 of 28 outline dimensions figure 42 . 16 - lead thin shrink small outline with exposed pad [tssop_ep] (re - 16 - 4) dimension s shown in millimeters ordering guide model 1 temperature range package description package option packing adp2381arez -r7 ?40c to +125c 16 - lead tssop_ep re -16 -4 reel adp2381arez ?40c to +125c 16 - lead tssop_ep re -16 -4 tube adp2381 - evalz evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-153-abt 08-03-2010-a 16 9 8 1 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bottom view top view 9 16 1 8 pin 1 indicator 4.50 4.40 4.30 5.10 5.00 4.90 3.40 2.68 2.46 1.75 exposed pad 1.10 max seating plane 0.15 max 0.05 min coplanarity 0.076 0.95 0.90 0.85 0.30 0.19 0.65 bsc 0.20 0.09 0.25 8 0 0.70 0.60 0.50 6.40 bsc ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10209 -0- 3/12(0)

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